Title :
An enhanced area-efficient on-chip compensation technique for power converters
Author :
Peng Sun ; Menglian Zhao ; Xiaobo Wu
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Abstract :
A novel high area-efficient on-chip lag (PI) compensation technique for power converters is proposed in this paper. This technique combined current-mode with voltage-mode capacitor multiplier. The compensation capacitor can be reduced to smaller than 10% of the conventional one. This proposed technique is successfully verified by a boost converter system with current program mode (CPM) control. The system proves to be stable for loading conditions from 100mA to 300mA. While conventional compensation capacitor and resistor are 30pF and 2.5MΩ, the proposed technique needs only 3pF and 1.2MΩ consuming 8μA extra current.
Keywords :
DC-DC power convertors; capacitors; compensation; power convertors; voltage multipliers; CPM control; DC-DC converterr; PI compensation technique; capacitance 3 pF; capacitance 30 pF; combined current-mode capacitor multiplier; compensation capacitor; current 100 mA to 300 mA; current 8 muA; current program mode control; enhanced area-efficient on-chip lag compensation technique; power converters; resistance 1.2 Mohm; resistance 2.5 Mohm; resistor; voltage-mode capacitor multiplier; Capacitors; Equations; Light emitting diodes; Resistors; System-on-chip; Topology; Capacitor multiplier; DC-DC converterr; PI compensation; Type II compensator; on-chip compensation;
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
DOI :
10.1109/EDSSC.2012.6482829
