Title :
Design and verification of a novel multi-RC-triggered power clamp circuit for on-chip ESD protection
Author :
Guangyi Lu ; Yuan Wang ; Jian Cao ; Qi Liu ; Xing Zhang
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China
Abstract :
A novel multi-RC-triggered power clamp circuit is proposed in this paper. Effective capacitances of capacitors are multiplied by current mirrors and a modified asymmetric phase inverter is employed in the proposed circuit. Simulation and test results verify that the proposed circuit maintains enhanced ESD protection robustness with reduced chip-area.
Keywords :
current mirrors; electrostatic discharge; integrated circuit design; invertors; current mirrors; electrostatic discharge; modified asymmetric phase inverter; multiRC-triggered power clamp circuit; on-chip ESD protection; Clamps; Electrostatic discharges; Inverters; Layout; Logic gates; Mirrors; Transistors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th
Conference_Location :
Las Vegas, NV
