Title :
A 20Gbps on-chip transceiver with equalization technique for global signal transmission
Author :
Wei Mo ; Keng Chen ; Yi Liu ; Qi Wang
Author_Institution :
Key Lab. of the Minist. of Educ. for Wide Band-Gap Semicond., Xidian Univ., Xi´an, China
Abstract :
In order to achieve high-speed and low-power signal transmission in long interconnection of Network on Chip (NoC), the performance of co-planar differential transmission line (DTL) is analyzed by HFSS in this paper. Current Mode Logic (CML) transmitter and Continuous-Time Linear Equalizer (CTLE) are adopted to reduce the impact of line loss and inter-symbol interference (ISI). Simulation results by Spectre show that the transceiver can transmit 20Gbps data through 10mm DTL in 130nm standard CMOS process, the unit power is only 0.44pj/bit.
Keywords :
coplanar transmission lines; current-mode logic; intersymbol interference; network-on-chip; transceivers; CML transmitter; CMOS process; HFSS; ISI; NoC; Spectre; bit rate 20 Gbit/s; continuous-time linear equalizer; coplanar differential transmission line; current mode logic transmitter; equalization technique; global signal transmission; intersymbol interference; line loss; network on chip; on-chip transceiver; size 130 nm; CML; CTLE; NoC; transmission line;
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
DOI :
10.1109/EDSSC.2012.6482834
