Test structures to investigate thin insulator dielectric wearout and breakdown

A study of the dependence of thin dielectric wearout and breakdown on capacitor geometry was undertaken. A test chip was designed and fabricated with thin silicon oxides using different gate-metal processes. The breakdown voltage distributions as a function of area, perimeter, and process variations were measured. It was found that the intrinsic breakdown voltage depended on details of the capacitor geometry and gate processing. The wearout of the oxide was apparently independent of area. It was shown that ramp current-voltage testing was useful for characterizing a thin oxide process and for determining when edge effects were important