Title :
A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver
Author :
Hirabayashi, O. ; Kawasumi, A. ; Suzuki, A. ; Takeyama, Y. ; Kushida, K. ; Sasaki, T. ; Katayama, A. ; Fukano, G. ; Fujimura, Y. ; Nakazato, T. ; Shizuki, Y. ; Kushiyama, N. ; Yabe, T.
Author_Institution :
Toshiba Semicond., Kawasaki
Abstract :
A 512 Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179 mum2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.
Keywords :
CMOS memory circuits; SRAM chips; driver circuits; CMOS; WL level-control scheme; adaptive WL-level programming scheme; cell failure rate; dual-power-supply SRAM; dynamic-array-supply control; level-programmable wordline driver; size 40 nm; storage capacity 512 Kbit; CMOS technology; Energy consumption; MOSFETs; Power generation; Power supplies; Random access memory; Regulators; Solid state circuits; Very large scale integration; Voltage;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977506
