Title :
Impact of the on-chip and off-chip ESD protection network on transient-induced latch-up in CMOS IC
Author :
Scholz, Matthias ; Shih-Hung Chen ; Hellings, Geert ; Linten, D.
Author_Institution :
Dept. ELEC, Vrije Univ. Brussels, Brussels, Belgium
Abstract :
Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; integrated circuit testing; CMOS integrated circuits; TLU; active clamp; electrostatic discharge; off-chip ESD protection network; on-chip ESD protection network; on-chip decoupling; parasitic SCR; transient-induced latch-up; Capacitors; Clamps; Electrostatic discharges; Hidden Markov models; Stress; Thyristors; Voltage measurement;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013 35th
Conference_Location :
Las Vegas, NV
