Optimized MAC unit design

Author

Deepak, S. ; Kailath, Binsu J.

Author_Institution

Indian Inst. of Inf. Technol. Design & Manuf., Chennai, India

fYear

2012

Firstpage

1

Lastpage

4

Abstract

In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case. From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers.

Keywords

adders; logic design; multiplying circuits; Kogg tone adder; MAC unit design; array multipliers; booth multipliers; different adders; multiplier accumulator unit; multiplier design; power dissipation; propagation delay; Adders; Arrays; Educational institutions; Power demand; Power dissipation; Propagation delay; Simulation; MAC Unit; Propagation delay; RTL Compiler; multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on

Conference_Location

Bangkok

Print_ISBN

978-1-4673-5694-7

Type

conf

DOI

10.1109/EDSSC.2012.6482843

Filename

6482843