Title :
Noise performance optimization design for high-speed analog-to-digital converters
Author :
Sandage, Robert W. ; Burns, Stanley G.
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
An fT=8.5 GHz NPN bipolar junction transistor (BJT)-based application specific integrated circuit (ASIC) comparator, for use in analog-to-digital converters (ADCs) is designed for optimum noise performance using process-derived model parameters including base spreading resistance, device geometry, and spot noise figure contours. The relationship between sensitivity of the comparator and equivalent input noise (Eni) and offset voltage (VOS) is presented. Eni and VOS must be minimized for a high-resolution comparator. An equivalent input noise voltage of less than 1.2 nV/√Hz is predicted and measured, which is approximately 1/3 that obtained from typical low-noise ADC comparators
Keywords :
analogue-digital conversion; application specific integrated circuits; bipolar integrated circuits; circuit CAD; comparators (circuits); linear integrated circuits; random noise; semiconductor device noise; 8.5 GHz; BJT-based ASIC; NPN bipolar junction transistor; QuicKic; TEKSPICE; analog-to-digital converters; application specific integrated circuit; base spreading resistance; device geometry; equivalent input noise; flash ADC; high speed ADC; high-resolution comparator; low-noise ADC comparators; noise performance optimisation design; offset voltage; optimum noise performance; process-derived model parameters; sensitivity; spot noise figure contours; Analog-digital conversion; Application specific integrated circuits; Bipolar transistor circuits; Computational geometry; Integrated circuit modeling; Integrated circuit noise; Noise figure; Optimization; Solid modeling; Voltage;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271245
