Title :
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM
Author :
Niitsu, Kiichi ; Shimazaki, Yasuhisa ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Kasuga, Kazutaka ; Nonomura, Itaru ; Saen, Makoto ; Komatsu, Shigenobu ; Osada, Kenichi ; Irie, Naohiko ; Hattori, Toshihiro ; Hasegawa, Atsushi ; Kuroda, Tadahiro
Author_Institution :
Keio Univ., Yokohama
Abstract :
This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90 nm CMOS 8-core processor, back-grinded to a thickness of 50 mum, is mounted face down on a package by C4 bump. A 65 nm CMOS 1 MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2 Gb/s data link. Measured power and area efficiency of the link is 1 pJ/b and 0.15 mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; integrated circuit packaging; CMOS 8-core processor 3D integration; CMOS SRAM chip; bit rate 19.2 Gbit/s; circuit package; inductive-coupling link; power measurement; size 50 mum; size 65 nm; size 90 nm; three-dimensional system integration; CMOS process; Coupling circuits; Inductors; Interference; Power dissipation; Random access memory; Registers; Space vector pulse width modulation; Timing jitter; Voltage control;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977517
