Title :
CMOS cells for analog VLSI Laplace equation solver based on the resistive analogy method
Author :
Ramirez-Angulo, Jaime ; DeYong, Mark ; Ming-Sheng, Sun
Author_Institution :
New Mexico State Univ., Las Cruces, NM, USA
Abstract :
An analog VLSI Laplace equation solver is described. The system uses MOS transistors in ohmic mode to simulate a resistive grid of cells similar to the resistive analogy method used for solving the Laplace equation. The VLSI circuit is a two-dimensional array of cells, each of which can be configured digitally to simulate a resistive or a boundary cell. The CMOS cell implementation and the overall system architecture are discussed
Keywords :
CMOS integrated circuits; VLSI; analogue processing circuits; cellular arrays; CMOS cell implementation; Laplace equation solver; analog; ohmic mode; overall system architecture; resistive analogy method; resistive grid; two-dimensional array; Boundary conditions; Buffer storage; Decoding; Inverters; Laplace equations; Logic; Switches; Variable structure systems; Very large scale integration; Voltage control;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271252
