Mixed-mode simulation for time-domain fault analysis

The issue of testing mixed-mode (analog-digital) ASICs (application-specific integrated circuits) is considered. The author describes a uniform mixed-mode simulation environment which allows a selection of the level of modeling for both analog and digital macros and includes and implementation involving the concurrent operation of hardware accelerators for both analog and digital simulation. In addition, methodology for mixed-mode-test generation is proposed based on time-domain simulation of faulted analog macros in situ, with surrounding macros being modeled at the device level or the behavioral level. This proposal includes suggested fault categories, transient-waveform generation techniques, and some suggestions pertaining to the controllability and observability of analog macros, including a proposal for an analog scan chain. An example is given in the form of a recording channel design, whose major control loop contains around 500 analog devices, as well as enough digital function to obviate an all-analog simulation