Title :
A review on low-voltage BiCMOS circuits and a BiCMOS vs. CMOS speed comparison
Author :
Sakurai, Takayasu
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
Proposals on low-voltage BiCMOS basic logic gates are reviewed, and low-voltage BiCMOS speed is compared with CMOS speed. In relation to the BiCMOS vs. CMOS speed comparison, it is shown that the gate delay at fanout of about 5 is a good measure of the relative delay of CMOS/BiCMOS optimized buffers. Analyzing 3.3-V BiCMOS macro as an example, it is shown that the most notable speed merit of 0.5-μm BiCMOS comes from emitter-coupled logic (ECL)-like circuits such as bipolar comparators and bipolar hit logic in cache macros
Keywords :
BiCMOS integrated circuits; comparators (circuits); integrated logic circuits; logic gates; CMOS; bipolar comparators; bipolar hit logic; delay; emitter-coupled logic; fanout; gate delay; logic gates; low-voltage BiCMOS circuits; macro; speed comparison; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Capacitance; Delay; Logic gates; Proposals; Semiconductor device modeling; Semiconductor devices; Voltage;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271261
