VLSI design of a systolic array for finding maximal overlaps of strings

The shortest common superstring (SCS) problem requires that the maximal overlays between a given set of strings be found. An efficient VLSI design of a systolic array for finding maximal overlays of strings is described. The systolic array consists of two types of cells, comparator and accumulator. The comparator cell is a combinational circuit, and the accumulator cell is sequential. Inverting half shift register stages are used to move the streams. Therefore two versions (positive and negative) of each of the two cells are needed. The positive accumulator cell circuit and cell layout are illustrated. Alternate cells in the systolic array are clocked by a different phase of a two-phase nonoverlapping clock