Analog operation in CMOS latch circuit for reducing dynamic power dissipation

An optimization technique for reducing the dynamic power dissipation of CMOS static latch circuits is presented using analog operation techniques. The latches are desirable for signal processing applications. The two-phase static latch is a gate model which is selected for the quality of data transfer. The structure employs a two-phase clocking arrangement with high-clock frequency. The structure is similar to true single-phase-clock latch stages and improves speed performance