Title :
Analog operation in CMOS latch circuit for reducing dynamic power dissipation
Author :
Dejhan, K. ; Cheevasuvit, F. ; Tipsuwanporn, V. ; Trisuwannawat, T. ; Prommas, E.
Author_Institution :
Fac. of Eng., King Mongkut´´s Inst. of Technol., Bangkok, Thailand
Abstract :
An optimization technique for reducing the dynamic power dissipation of CMOS static latch circuits is presented using analog operation techniques. The latches are desirable for signal processing applications. The two-phase static latch is a gate model which is selected for the quality of data transfer. The structure employs a two-phase clocking arrangement with high-clock frequency. The structure is similar to true single-phase-clock latch stages and improves speed performance
Keywords :
CMOS integrated circuits; analogue processing circuits; CMOS latch circuit; analog operation techniques; data transfer; dynamic power dissipation; gate model; optimization technique; signal processing applications; speed performance; two-phase clocking; Application specific integrated circuits; CMOS analog integrated circuits; CMOS technology; Clocks; Latches; MOSFETs; Power dissipation; Power engineering and energy; Shape; Signal processing;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271266
