Title :
A VLSI architecture for automatic speech recognition on large vocabularies
Author :
Hauenstein, Alfred
Abstract :
The VLSI architecture of a coprocessor for automatic speech recognition is presented. The processor is capable of executing the most computationally intensive task in speech recognition, the Viterbi-search for word- and sentence-hypotheses, in real-time. This is achieved by a specialized arithmetic unit (AU) and an application specific memory architecture. The arithmetic core attains a clock frequency of more than 50 MHz and consists of 14000 transistors. The memory architecture excels by a highly parallelized memory access enabled by three independent address units and a memory bandwidth of 266 MByte/s
Keywords :
VLSI; digital arithmetic; memory architecture; parallel architectures; speech recognition equipment; 266 B/s; VLSI architecture; Viterbi-search; address units; application specific memory architecture; arithmetic core; automatic speech recognition; clock frequency; computationally intensive task; coprocessor; large vocabularies; parallelized memory access; sentence-hypotheses; specialized arithmetic unit; word-hypotheses; Arithmetic; Automatic speech recognition; Clocks; Computer architecture; Coprocessors; Frequency; Gold; Memory architecture; Speech recognition; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
DOI :
10.1109/MWSCAS.1992.271267
