Title :
28V ESD clamp in CMOS 40nm process
Author :
Chowdary, G. ; Neri, Ferrante ; Somajayula, S. ; Notermans, G.
Author_Institution :
Aura Semicond., Bangalore, India
Abstract :
The thin gate oxide in nanoscale CMOS technologies is a serious challenge to the electrostatic discharge (ESD) robustness of ICs. This paper describes a sophisticated design solution for a 28V ESD clamp integrated in a 40nm CMOS product using only 2.75V transistors. It is suitable for I/O interface in SoC chips for mobile application and allows a battery charger to be connected directly to the chip. The presented clamp passed ESD/Latch-up test for HBM 3KV, 30V over-voltage test and 1000-hours prolonged operation life-time test.
Keywords :
CMOS integrated circuits; electrostatic discharge; system-on-chip; CMOS process; ESD clamp; I/O interface; SoC chips; electrostatic discharge; integrated circuits; mobile application; nanoscale CMOS technologies; size 40 nm; thin gate oxide; voltage 28 V; CMOS integrated circuits; CMOS technology; Clamps; Electrostatic discharges; Logic gates; System-on-chip; Transistors; 28V; 40nm CMOS; Human-Body Model (HBM); electrostatic discharge (ESD); gate oxide over-stress; on-chip ESD protection;
Conference_Titel :
Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5694-7
DOI :
10.1109/EDSSC.2012.6482885
