Title :
Evaluation of power gating under transistor aging effect issues in 22nm CMOS technology
Author :
Liu, Luchuan ; Mahmoodi, Hamid
Author_Institution :
Sch. of Eng., San Francisco State Univ., San Francisco, CA, USA
Abstract :
Power gating is an effective low-power design technique and is the most widely adopted leakage current reduction solution. In this project, we evaluate the effectiveness of power gating in 22 nm CMOS and analyze the impacts of the Positive/Negative Bias Temperature Instability (PBTI/NBTI) phenomenon on the power gating technique. We also estimate the actual temperatures of power gated circuits and simulate them under different temperatures. The results show that power gating can reduce the effect of PBTI/NBTI, effectively save power, and reduce temperature and delay in hospitable situations while it may not be a good choice in all cases.
Keywords :
CMOS integrated circuits; ageing; integrated circuit reliability; leakage currents; low-power electronics; semiconductor device reliability; transistors; CMOS technology; NBTI; PBTI; leakage current reduction solution; negative bias temperature instability; positive bias temperature instability; power gating evaluation; power saving; reliability; size 22 nm; temperatures estimation; transistor aging; Aging; Delay; Leakage current; Logic gates; Reliability; Stress; Transistors; Power gating; delay; power; sleep; temperature;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference
Conference_Location :
Warsaw
Print_ISBN :
978-1-4244-7011-2
Electronic_ISBN :
978-83-928756-4-2
