Quarter-square analog four-quadrant multiplier based on CMOS invertes and using low voltage high speed control circuits

This paper concerns a quarter-square analog four-quadrant multiplier, based on proprietary architecture using four CMOS inverters. The most important difference with respect to already published own circuit implementation is the use of inverter `core´ of the circuit with completely redesigned auxiliary and steering blocks. The proposed circuit solution is suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.