DocumentCode :
1620578
Title :
A Multi Gigabit FPGA-Based 5-tuple Classification System
Author :
Nikitakis, A. ; Papaefstathiou, I.
Author_Institution :
Dept. of Electron. & Comput. Eng., Tech. Univ. of Crete, Chania
fYear :
2008
Firstpage :
2081
Lastpage :
2085
Abstract :
Packet classification is one of the most important enabling technologies for next generation network services. Even though many multi-dimensional classification algorithms have been proposed, most of them are precluded from commercial equipments due to their high memory requirements. In this paper, we present an efficient packet classification scheme, called dual stage bloom filter classification engine (2sBFCE). 2sBFC comprises of an innovative 5- field search scheme that decomposes multi-field classification rules into internal single-field rules which are combined using multi-level Bloom filters. The design of 2sBFCE is optimized for the common case based on analysis of real world classification databases. The hardware implementation of this scheme handles 4 K rules while supporting network streams at a rate of 2 Gbps even in the worst case, and more than 6 Gbps in the average case when implemented in an off-the-shelf FPGA.
Keywords :
field programmable gate arrays; information filters; 2sBFCE; 5-tuple classification system; FPGA; dual stage bloom filter classification engine; field programmable gate arrays; multilevel Bloom filters; packet classification; Classification algorithms; Communications Society; Computer networks; Costs; Engines; Field programmable gate arrays; Hardware; Matched filters; Next generation networking; Quality of service;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, 2008. ICC '08. IEEE International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2075-9
Type :
conf
DOI :
10.1109/ICC.2008.399
Filename :
4533435
Link To Document :
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