DocumentCode
1620629
Title
Ultra-thin body Silicon On Insulator and nanowire transistors for 22nm technology node and below
Author
Poiroux, Thierry ; Andrieu, François ; Weber, Olivier ; Dupré, Cécilia ; Ernst, Thomas ; Fenouillet-Beranger, Claire ; Perreau, Pierre ; Buj-Dufournet, Christel ; Tosti, Lucie ; Brevard, Laurent ; Barraud, Sylvain ; Faynot, Olivier
Author_Institution
Dept. of Nanotechnol., CEA-LETI/Minatec, Grenoble, France
fYear
2010
Firstpage
30
Lastpage
34
Abstract
We demonstrate that Fully Depleted Silicon-On-Insulator (FDSOI) technology is a simple and mature alternative to the bulk one for the 22nm technology node and beyond. In particular, this technology allows significant improvement of the transistors electrostatic control and variability. Furthermore, the integration of such FDSOI transistors on an ultra-thin buried oxide allows their scalability down to 10nm gate lengths and enables an efficient use of power management techniques. We also illustrate some technological ways to boost the drive current of these devices. Finally, we present a 3D-stacked nanowire architecture as a solution to extend the scaling to the sub-10nm technology nodes and to increase significantly the current supplied per layout unit area.
Keywords
nanowires; silicon-on-insulator; transistors; 3D-stacked nanowire architecture; CMOS scaling; FDSOI transistors; drive current; fully depleted silicon-on-insulator; nanowire transistors; power management techniques; size 10 nm; size 22 nm; technology nodes; transistors electrostatic control; ultra-thin buried oxide; Electrostatics; Films; Logic gates; Scalability; Silicon; Threshold voltage; Transistors; CMOS scaling; Silicon on insulator technology; nanowire technology; variability;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference
Conference_Location
Warsaw
Print_ISBN
978-1-4244-7011-2
Electronic_ISBN
978-83-928756-4-2
Type
conf
Filename
5551641
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