Exploring ESD challenges in sub-20-nm bulk FinFET CMOS technology nodes

Bulk FinFET is the main technology option for sub 20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsic ESD performance. In this work, the impact on ESD performance induced by the process options beyond 20 nm nodes is explored on different ESD devices. Furthermore, experimental results of SCR devices in bulk FinFET technology are demonstrated for the first time.