Improving stress effect and low noise design of the integrated on-panel TFT gate driver

In this paper, the reliable on-panel display gate driver is designed not only decreasing the fluctuation noise of the output signal, but also reducing the voltage stress effect of the dual pull-down transistors. The long-term high gate to source voltage causes the threshold voltage increased, and the fluctuation-noise on the output is coupled from the parasitical capacitance when the clock switches. Our work improved the stress effect of transistor of dual pull-down by reduced the controlled signal voltage and it maintained the anti-floating low noise structure. This gate driver was simulated by the Smart-SPICE level-35 for the α-Si TFT process model.