Design procedure for settling time minimization in three-stage RNMC amplifiers

Author

Afrancheh, Saeed Reza ; Arazm, Mohammad Reza ; Sahab, Ali Reza ; Afrancheh, Hamid Reza

Author_Institution

Lahijan Branch, Islamic Azad Univ., Lahijan, Iran

fYear

2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a new method in time domain for optimizing the settling time in three stage amplifiers with reversed nested Miller compensation (RNMC). This procedure allows the compensation capacitors to be sized to achieve the best settling behavior of the closed-loop op-amp. To show the effectiveness of the method, a typical amplifier in 1V, 90 nm CMOS technology is designed. Simulation results show that using this method, settling time of three-stage RNMC amplifiers significantly improved compared to conventional design method. Also, the figure of merit of this amplifier shows the ratio settling-time/power-consumption of amplifier is greater than the other NMC amplifiers.

Keywords

CMOS integrated circuits; integrated circuit design; operational amplifiers; transient response; CMOS technology; closed-loop operational amplifiers; compensation capacitors; conventional design method; power consumption; reversed nested Miller compensation; settling time minimization; size 90 nm; three-stage RNMC amplifiers; voltage 1 V; CMOS integrated circuits; Capacitors; Equations; Feedforward neural networks; Mathematical model; Simulation; Time domain analysis; Analog design; Three-stage amplifiers; reversed nestedMiller compensation; transient response;

fLanguage

English

Publisher

ieee

Conference_Titel

EUROCON - International Conference on Computer as a Tool (EUROCON), 2011 IEEE

Conference_Location

Lisbon

Print_ISBN

978-1-4244-7486-8

Type

conf

DOI

10.1109/EUROCON.2011.6174587

Filename

6174587