• DocumentCode
    1621101
  • Title

    Increasing processor performance by implementing deeper pipelines

  • Author

    Sprangle, Eric ; Carmean, Doug

  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    25
  • Lastpage
    34
  • Abstract
    One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper explores the relationship between performance and pipeline depth using a Pentium(R) 4 processor like architecture as a baseline, and shows that deeper pipelines can continue to increase the performance. This paper shows that the branch misprediction latency is the single largest contributor to performance degradation as pipelines are stretched, and therefore branch prediction and fast branch recovery will continue to increase in importance. We show that higher performance cores, implemented with longer pipelines, for example, will put more pressure on the memory system, and therefore require larger on-chip caches. Finally, we show that in the same process technology, designing deeper pipelines can increase the processor frequency by 100%, which, when combined with larger on-chip caches can yield performance improvements of 35% to 90% over a Pentium 4 like processor
  • Keywords
    microcomputers; performance evaluation; pipeline processing; Pentium processor; branch prediction; branch recovery; pipeline depth; pipeline processing; processor performance; Analytical models; Computer architecture; Degradation; Delay; Frequency; Microprocessors; Pipelines; Predictive models; Process design; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on
  • Conference_Location
    Anchorage, AK
  • ISSN
    1063-6897
  • Print_ISBN
    0-7695-1605-X
  • Type

    conf

  • DOI
    10.1109/ISCA.2002.1003559
  • Filename
    1003559