Effects of transistor reordering on the performance of MOS digital circuits

Author

Carlson, Bradley S. ; Chen, C. Y Roger

Author_Institution

Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

fYear

1992

Firstpage

121

Abstract

The effect of transistor reordering on the tuning behavior of MOS circuits is investigated. The investigation is performed by analyzing the transient response of series connected MOS structures (SCMSs) using SPICE. The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time. Circuits for which the effect of transistor reordering on timing is insignificant are clearly identified

Keywords

MOS integrated circuits; SPICE; circuit analysis computing; integrated logic circuits; logic gates; transient response; MOS digital circuits; MOS logic gate; SPICE; critical input signal transition time; load capacitance; series connected MOS structures; stack height; timing performance; transient response; transistor reordering; tuning behavior; CMOS logic circuits; Digital circuits; Integrated circuit synthesis; Integrated circuit technology; Logic circuits; Logic design; Logic gates; MOSFETs; Power dissipation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271318

Filename

271318