Integrated memory/network architectures for cluster-organized, parallel DSP architectures

The capabilities of switched networks for parallel and distributed computers are evolving rapidly towards networks with various forms of intelligence in support of parallel execution of programs. This paper presents a perspective on intelligent networks, including reconfiguration of the network to adapt to the needs of successive computational algorithms being performed as part of an overall problem, for clusters containing a modest number of digital signal processors (DSPs). Scalability of the overall parallel DSP-based computer is achieved by adding these cluster nodes. It is suggested that there are many operating system functions which might be directly integrated into such an intelligent network, including adapting those operating system functions according to the needs of the specific tasks being performed. The viewpoint presented here is based on a reconfigurable system using FPGAs and being constructed for image processing applications to study opportunities for integration of such intelligent networks into future silicon VLSI components, including advanced packaging such as multichip modules (MCMs). The packaging limitations present the greatest barrier to aggressive development of such networks, with active substrate MCM implementation of the network function providing the greatest flexibility and performance