Title :
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems
Author :
Stripf, T. ; Oey, O. ; Bruckschloegl, T. ; Koenig, R. ; Huebner, M. ; Becker, J. ; Goulas, G. ; Alefragis, P. ; Voros, N.S. ; Rauwerda, G. ; Sunesen, K. ; Derrien, S. ; Menard, D. ; Sentieys, O. ; Kavvadias, N. ; Dimitroulakos, G. ; Masselos, K. ; Goehrin
Author_Institution :
Karlsruhe Inst. of Technol., Karlsruhe, Germany
Abstract :
The mapping process of high performance embedded applications to today´s reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware - introduced by software parallelism of multiple cores and the flexibility of reconfigurable architectures - to the end user. The Architecture oriented paraLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab- and architecture-description-language-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development costs, and shorter time-to-market.
Keywords :
embedded systems; system-on-chip; Scilab; architecture-description-language-based toolchain; architecture-oriented parallelization; development cost reduction; high-performance embedded application; mapping process; multiple-core software parallelism; power consumption; reconfigurable architecture flexibility; reconfigurable multicore embedded system; reconfigurable multiprocessor; simplified programming process; system-on-chip devices; time-to-market; underlying hardware complexity; Digital signal processing; Multicore processing; Optimization; Parallel processing; Program processors; Tiles;
Conference_Titel :
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on
Conference_Location :
York
Print_ISBN :
978-1-4673-2570-7
Electronic_ISBN :
978-1-4673-2571-4
DOI :
10.1109/ReCoSoC.2012.6322879