Title :
ENOSYS FP7 EU project: An integrated modeling and synthesis flow for embedded systems design
Author :
Brosse, Etienne ; Quadri, Imran R. ; Sadovykh, Andrey ; Ieromnimon, Frank ; Kritharidis, Dimitrios ; Catrou, Rafaël ; Sarlotte, Michel
Author_Institution :
Softeam, Paris, France
Abstract :
The ENOSYS project, funded by the EC, aims to shorten the time-to-market of high-performance SoCs by providing design and tool flows for the design and the implementation of embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis, code optimization and design space exploration. The objective here is to automatically generate code, for implementation in execution platforms such as FPGAs, from validated high level designs incorporating initial end user requirements, system functional and non-functional description, platform modelling. This paper describes the design flow developed in the context of the ENOSYS project and the results of a first industrial evaluation through two industrial test cases.
Keywords :
embedded systems; field programmable gate arrays; logic design; program compilers; system-on-chip; ENOSYS FP7 EU project; FPGA; SoC; code optimization; design space exploration; embedded systems design; hardware synthesis; high-level system; integrated modeling; software code generation; synthesis flow; system-on-chip; time-to-market; Embedded systems; Hardware; Optimization; Space exploration; Transform coding; Unified modeling language; Design space exploration; MARTE; Real-Time Embedded Systems Modeling; Synthesis; UML;
Conference_Titel :
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on
Conference_Location :
York
Print_ISBN :
978-1-4673-2570-7
Electronic_ISBN :
978-1-4673-2571-4
DOI :
10.1109/ReCoSoC.2012.6322880
