RISP: A digital signal processor architecture with reduced instruction set tailored to wave digital filters

Author

Kaiser, Ulrich ; Sandner, Harald

Author_Institution

Texas Instrum. Deutschland GmbH, Freising, Germany

fYear

1992

Firstpage

32

Abstract

VLSI in digital signal processing requires small, stable, high-speed infinite impulse response (IIR) filters. A novel DSP architecture, RISP (reduced instruction set processor), has been designed. It incorporates a reduced-instruction set to minimize instruction cycle time, a three-stage pipeline, small transistor count and specialized blocks enabling high throughput for wave digital filter (WDF) algorithms, including decimation and interpolation. The RISP architecture has been verified by means of a dedicated CAD system including the top-down design of lattice WDFs from specification to RISP machine code

Keywords

VLSI; digital signal processing chips; pipeline processing; reduced instruction set computing; wave digital filters; DSP architecture; RISP; VLSI; decimation; dedicated CAD system; digital signal processor architecture; infinite impulse response; instruction cycle time; interpolation; lattice WDFs; reduced instruction set; three-stage pipeline; throughput; top-down design; wave digital filters; Digital filters; Digital signal processing; Digital signal processors; IIR filters; Interpolation; Pipelines; Process design; Signal processing algorithms; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271341

Filename

271341