• DocumentCode
    1622013
  • Title

    Symbolic model checking of dual transition Petri Nets

  • Author

    Varea, Mauricio ; Al-Hashimi, B.M. ; Cortés, Luis A. ; Eles, Petru ; Peng, Zebo

  • Author_Institution
    Dept. of Electron. & Comput. Sci., Southampton Univ., UK
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    43
  • Lastpage
    48
  • Abstract
    This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models, using model checking techniques. The methodology presented addresses the Symbolic model checking of embedded systems behavioural properties, expressed in either computation tree logics (CTL) or linear temporal logics (LTL). The embedded system specification is given in terms of DTPN models. where elements of the model are captured in a four-module library which implements the behaviour of the model. Key issues in the development of the methodology are the heterogeneity and the nondeterministic nature of the model. This is handled by introducing some modifications in both structure and behaviour of the model, thus reducing the points of nondeterminism. Several features of the methodology are discussed and two examples are given in order to show the validity of the model
  • Keywords
    Petri nets; embedded systems; formal specification; formal verification; computation tree logics; dual transition Petri nets; embedded systems; formal verification; linear temporal logics; model checking techniques; symbolic model checking; Computer science; Ear; Embedded computing; Embedded system; Formal verification; Libraries; Logic design; Permission; Petri nets; State-space methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign, 2002. CODES 2002. Proceedings of the Tenth International Symposium on
  • Conference_Location
    Estes Park, CO
  • Print_ISBN
    1-58113-542-4
  • Type

    conf

  • DOI
    10.1109/CODES.2002.1003599
  • Filename
    1003599