DocumentCode :
1622049
Title :
Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments
Author :
Bekiaris, Dimitris ; Sotiriou-Xanthopoulos, Efstathios ; Economakos, George ; Soudris, Dimitrios
Author_Institution :
Digital Syst. Lab., Nat. Tech. Univ. of Athens, Athens, Greece
fYear :
2012
Firstpage :
1
Lastpage :
8
Abstract :
Modern digital design has been greatly forced to offer More-Moore integration densities and very high operation frequencies for demanding applications. In this search-for-performance race, alternative and less radical More-than-Moore solutions are emerging, like reconfigurable computing. Reconfigurable computing stands between hardware and software and promises to offer the former´s performance alongside with the latter´s flexibility. Research in the field deals with fine or coarse grain reconfigurable components and efficient ways to map applications onto them. In this paper, a systematic design methodology and evaluation of a coarse grain reconfigurable component targeting the ASIC domain is presented. The specific component is a morphable architecture, that works in mutually exclusive modes, offering different functionality in each mode. The novelty presented in this paper is a systematic evaluation of the scalability of the morphable component. Continuously functionally improved modes are evaluated for performance, area and power, in order to choose the best architecture for a number of widely used DSP applications. Overall, a power* performance improvement of up to 24% is reported and a power* area of up to 13% compared to conventional, non-reconfigurable component architectures.
Keywords :
application specific integrated circuits; logic design; multiplying circuits; ASIC domain; DSP applications; HLS environments; More-Moore integration density; coarse grain reconfigurable components; digital design; high-level synthesis; nonreconfigurable component architectures; radical More-than-Moore solutions; reconfigurable computing; scalable reconfigurable multiplier scheme; systematic design; systematic design methodology; Adders; Computer architecture; Hardware; Microprocessors; Multiplexing; Optimization; Timing; design methodologies; high-level synthesis; reconfigurable computing; reconfigurable multiplier; runtime reconfiguration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on
Conference_Location :
York
Print_ISBN :
978-1-4673-2570-7
Electronic_ISBN :
978-1-4673-2571-4
Type :
conf
DOI :
10.1109/ReCoSoC.2012.6322890
Filename :
6322890
Link To Document :
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