Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoC) is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified by the improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present a communication-centric metric for high level 3D NoCs synthesis, which can be used to improve the system performance and to reduce the link heat degree significantly by distributing the communication evenly in the system. We take several state-of-the-art benchmarks and the generic scalable pseudo application (GSPA) with different network sizes for experiments, by combining the simulated annealing algorithm with the presented metric. In comparison to the well-know metrics (dynamic communication energy aware and contention count), our metric can generally maintain the system performance and achieve up to 48% advantage on the aspect of Hottest Link Degree. All the experiments have been done in SystemC-RTL, which can achieve the cycle accuracy.