Embedded UML design flow to the configurable LE1 MultiCore VLIW processor

This paper presents a tool-supported UML design flow (ENOSYS flow) for designing and implementing embedded systems through the seamless integration of high-level system specification, hardware synthesis, embedded soft VLIW multi-core processors and design space exploration. Using the proposed design flow, investigations into the tradeoffs between various multi-core processor parameters such as the issue width of the VLIW cores and the number of processor cores are performed. Many design permutations of the multiprocessor are automatically synthesised for a Virtex 6 FPGA board and design characteristics extracted. An example DES UML model was taken through the developed design flow and executed on a retargetable multi-core simulator to assess performance figures. The resulting binaries are verified by running on the generated bit streams downloaded on the target FPGA board.