Test generation for logic simulation based on functional graph

Logic simulation is the principal tool used to detect design errors at the logic design stage. Its effectiveness depends on the quality of the test patterns. The problem of test generation for initial logic simulation is addressed. In the authors´ method, a functional graph is introduced to describe the function to be implemented. The test patterns are generated to verify the functions of the nodes in a functional graph. Experimental results show that these test patterns have a high ability for design error detection, and can be easily generated in a short time