Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints

We are proposing a system level approach for a fault tolerant heterogeneous multi-processor system-on-chip (HMPSoC) platform that can be customized at design phase according to the requirements and the environmental constraints of the target application. This framework can provide optimal tradeoffs for maximizing the reliability of the system under real-time constraints. The proposed heterogeneous platform consists of a mesh-based network-on-chip (NoC) communication architecture, which is equipped with two different types of processing elements: (i) high fault tolerance (FT) and (ii) high performance (HP) processors. For critical applications, the designer can increase the proportion of fault tolerant processors in the HMPSoC in order to minimize the probability of failure by compromising the overall performance. Similarly, for less critical applications, the overall performance will increase by having a higher ratio of high performance processors. We will analyze the proposed HMPSoC architecture under different faults and performance constraints, so that the precise proportion of the diverse processors may be adjusted. The design space exploration has been carried out using our system-level design tool and the resulting schedules have been verified by executing the applications on cycle-accurate XHiNoC simulator. The objective of this approach is to generate a dependable system under hard real-time constraints with minimized hardware effort related to the adopted processing elements.