DocumentCode
1622517
Title
Translating affine nested-loop programs with dynamic loop bounds into Polyhedral Process Networks
Author
Nadezhkin, Dmitry ; Nikolov, Hristo ; Stefanov, Todor
Author_Institution
Leiden Inst. of Adv. Comput. Sci., Leiden Univ., Leiden, Netherlands
fYear
2010
Firstpage
21
Lastpage
30
Abstract
The Process Network (PN) is a suitable parallel model of computation (MoC) used to specify embedded streaming applications in a parallel form facilitating the efficient mapping onto embedded parallel execution platforms. Unfortunately, specifying an application using a parallel MoC is very difficult and highly error-prone task. To overcome the associated difficulties, an automated procedure exists for derivation of a specific polyhedral process networks (PPN) from static affine nested loop programs (SANLPs). This procedure is implemented in the pn complier. However, there are many applications, e.g., multimedia applications (MPEG coders/decoders, smart cameras, etc.) that have adaptive and dynamic behavior which can not be expressed as SANLPs. Therefore, in order to handle more dynamic multimedia applications, in this paper we address the important question whether we can relax some of the restrictions of the SANLPs while keeping the ability to perform compile-time analysis and to derive PPNs. Achieving this would significantly extend the range of applications that can be parallelized in an automated way. The main contribution of this paper is a first approach for automated translation of affine nested loops programs with dynamic loop bounds into input-output equivalent polyhedral process networks.
Keywords
embedded systems; multimedia computing; parallel processing; program compilers; affine nested loop program translation; automated procedure; compile time analysis; dynamic loop bound; dynamic multimedia applications; embedded parallel execution platform; embedded streaming applications; highly error prone task; input-output equivalent polyhedral process networks; parallel MoC; pn complier; polyhedral process networks; static affine nested loop programs; Algorithm design and analysis; Arrays; Heuristic algorithms; Image edge detection; Parallel processing; Upper bound; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Systems for Real-Time Multimedia (ESTIMedia), 2010 8th IEEE Workshop on
Conference_Location
Scottsdale, AZ
Print_ISBN
978-1-4244-9084-4
Type
conf
DOI
10.1109/ESTMED.2010.5666977
Filename
5666977
Link To Document