DocumentCode
1622810
Title
Practical test strategies for users of 100 p.p.m. ICs
Author
Westover, James H.
fYear
1989
Firstpage
295
Lastpage
303
Abstract
It is noted that in 1980s, integrated circuit suppliers have made major improvements in their product quality. As a result, users are receiving large volumes of devices with failure rates of less than 100 p.p.m.. This has provided users with alternatives to 100% testing, such as dock-to-stock and just-in-time programs. Although the quality of devices has improved, lots with reject rates exceeding 10000 p.p.m. continue to be reported. The author presents test results that demonstrate that quality variations from suppliers continue to occur. It is concluded that users should consider current results and carefully develop, from the many strategies available, their own strategies for reducing test costs while minimizing the risk of accepting defective devices. A number of test strategies and their applications are outlined
Keywords
economics; integrated circuit testing; integrated logic circuits; integrated memory circuits; quality control; IC testing; logic IC; memory IC; product quality; test costs; test strategies; Circuit testing; Computer aided manufacturing; Costs; Electronic equipment manufacture; Electronic equipment testing; Integrated circuit testing; Logic circuits; Logic devices; Logic testing; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/TEST.1989.82311
Filename
82311
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