UML profile for estimating application Worst Case Execution Time on System-on-Chip

Systems-on-chip (SOC) design is confronted with the problem of the so-called productivity gap. In order to cope with this problem, authors emphasize on using the unified modeling language (UML) as a system level language, so higher level of abstraction is achieved. In this context, we present a UML profile and a methodology for estimating application worst case execution time (WCET) on SOC. The proposed profile allows the designer to express hierarchy among application tasks, and most of parallelism forms that exist in typical embedded applications such as task parallelism, pipelining, and data parallelism, while making control and communication over tasks explicit. In order to estimate application WCET, the hardware platform on which application is mapped on, should be abstracted too. Consequently, each hardware component is parameterized by a set of parameters matching the abstraction level of the application. A particularity of our flow is that it starts by establishing a sequential object model using UML sequence diagram, from which a task-level model is extracted. We think that the sequential model is strongly preferred from the system designerpsilas perspective for two reasons. First, because it facilitates the modelling task relieving the designer of the burden of concurrency modelling. Secondly, starting from an existing sequential model (e.g. legacy C code) which is generally considered as the reference model, we can then parallelize it, and explore the design space. We show how we have used our profile for H264 decoder modeling.