Title :
Understanding models of substrate behaviour for the routing of high I/O packages
Author :
Palmer, P.J. ; Williams, D.J.
Author_Institution :
Dept. of Manuf. Eng, Loughborough Univ., UK
Abstract :
This paper explores two models of substrate wireability and examines the implications of these models in the forecast of the application of future generation integrated circuits and their packages, especially emerging generations of chip scale packages (CSPs). This is in order to clarify our understanding of potential technology bottlenecks. This analysis shows how the demands of future generation high pin density packages, exemplified by the wireability demand of CSPs, drive substrates. The importance of routers for the efficient utilisation of substrates is also quantified by this analysis. This work continues research by the authors to attempt to understand the trends in bare and packaged chip interconnection
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit packaging; network routing; CSPs; bare chip interconnection; chip scale packages; high I/O packages; high pin density packages; integrated circuit packages; integrated circuits; packaged chip interconnection; routers; routing; substrate behaviour models; substrate utilisation; substrate wireability models; Application specific integrated circuits; Chip scale packaging; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Pulp manufacturing; Read only memory; Roads; Routing; Virtual manufacturing;
Conference_Titel :
IC/Package Design Integration, 1998. Proceedings. 1998 IEEE Symposium on
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-8433-X
DOI :
10.1109/IPDI.1998.663622
