ASIC design of 600Mbps 4×4 MIMO wireless LAN system

This paper shows the design and ASIC implementation of a 802.11n WLANs 4×4 MIMO OFDM PHY transceiver. The system supports the maximum data rate of 600Mbps. The MMSE-SQRD SIC MIMO decoder scheme, which has high BER performance and acceptable hardware cost, is implemented. To meet the required high throughput rate, parallel processing Scrambler/Descrambler, parallel processing BCC, and radix-4 soft-decision Viterbi decoder are implemented. To reduce the hardware cost, the OFDM modulation for both cases 64 and 128 subcarriers is performed by a single mode 128-point (I)FFT per stream. To reduce the system latency, the bit-reversed (I)FFT is implemented. Furthermore, many ideas of combining multi tasks in a single block are implemented to save the hardware resource and the system latency. Our system is implemented in Synopsys CMOS SAED90nm process. The hardware resource cost by the main blocks of the system is exposed. In this paper, the detail description of system architecture is supposed to be useful for people who start to research and/or design the MIMO system.