Title :
Design for test of Mbit DRAMs
Author :
Kraus, Rainer ; Kowarik, Oskar ; Hoffmann, Karel ; Oberle, Dieter
Author_Institution :
Uni Bw Munich, West Germany
Abstract :
The authors describe a novel design for test of DRAMs (dynamic random-access memories) which speeds up testing during wafer sort and final test, even after repair by redundant bit lines. This concept is based on internal parallel and marginal tests initiated by a JEDEC (Joint Electron Device Engineering Council) conformance standard. Test sequences of 1-Mb and 4-Mb DRAMs were analyzed to determine the applicability and utility of the proposed test methods. Total test time savings range between 50% and 75%, depending on the memory size. The additional chip size is <1% of the total chip area
Keywords :
automatic testing; computer equipment testing; integrated circuit testing; integrated memory circuits; random-access storage; standards; 1 Mbit; 4 Mbit; DRAMs; JEDEC; conformance standard; dynamic random-access memories; internal parallel test; marginal tests; redundant bit lines; repair; test time savings; wafer sort; Automatic testing; Circuit faults; Circuit testing; Clocks; Content addressable storage; Costs; Logic testing; Random access memory; Size control; Test pattern generators;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82314
