• DocumentCode
    1623572
  • Title

    Balancing wrapper chains of SoC core based on best interchange decreasing

  • Author

    Yi, Maoxiang ; Liang, Huaguo ; Huang, Zhengfeng

  • Author_Institution
    Dept. of Electron. Sci. & Technol., Hefei Univ. of Technol., Hefei
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    An improved scheme for balancing wrapper chains partition of SoC core is proposed. Starting with the primary configuration created by LPT algorithm, we optimizes the current partition through the best interchange decreasing and iterative operation, in each step of which a pair of wrapper chains with maximum length difference is selected and the optimal two cells in the two wrapper chains are interchanged. Experiments are executed for the typical cores of the ITCpsila02 benchmarks. The results show that compared to the previous techniques, our scheme can create more balanced wrapper chains, decreasing the maximum scan shift length, hence the test application time of core.
  • Keywords
    iterative methods; system-on-chip; LPT algorithm; SoC core; best interchange decreasing; iterative operation; maximum length difference; maximum scan shift length; wrapper chains partition balancing; Application software; Automatic testing; Benchmark testing; Design for testability; Iterative algorithms; Logic testing; NP-hard problem; Partitioning algorithms; Switches; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip, 2008. SOC 2008. International Symposium on
  • Conference_Location
    Tampere
  • Print_ISBN
    978-1-4244-2541-9
  • Electronic_ISBN
    978-1-4244-2542-6
  • Type

    conf

  • DOI
    10.1109/ISSOC.2008.4694880
  • Filename
    4694880