DocumentCode :
1623599
Title :
A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects
Author :
Elrabaa, Muhammad E S
Author_Institution :
Comput. Eng. Dept., King Fahd Univ. of Pet. & Miner., Dhahran
fYear :
2008
Firstpage :
1
Lastpage :
4
Abstract :
A new delay-insensitive two-phase asynchronous handshaking protocol has been developed. The new protocol utilizes return to zero data format which simplifies communication circuits design significantly. Robust transceiver circuitry that implement this protocol have been developed and simulated using a 0.13mum, 1.2V technology to verify their performance.
Keywords :
asynchronous circuits; integrated circuit interconnections; system-on-chip; transceivers; asynchronous transceiver circuit; communication circuits design; delay-insensitive; pipe-lined SoC interconnects; return to zero data format; size 0.13 mum; transceiver circuitry; two-phase asynchronous handshaking protocol; voltage 1.2 V; Clocks; Communication system control; Delay; Integrated circuit interconnections; Network-on-a-chip; Pipeline processing; Protocols; Repeaters; Robustness; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip, 2008. SOC 2008. International Symposium on
Conference_Location :
Tampere
Print_ISBN :
978-1-4244-2541-9
Electronic_ISBN :
978-1-4244-2542-6
Type :
conf
DOI :
10.1109/ISSOC.2008.4694881
Filename :
4694881
Link To Document :
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