DocumentCode
1623661
Title
Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization
Author
Orsila, Heikki ; Salminen, Erno ; Hännikäinen, Marko ; Hämäläinen, Timo D.
Author_Institution
Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere
fYear
2008
Firstpage
1
Lastpage
6
Abstract
Design space exploration aims to find an energy-efficient architecture with high performance. A trade-off is needed between these goals, and the optimization effort should also be minimized. In this paper, we evaluate heterogeneous multiprocessor architectures by optimizing both energy and performance for applications. Ten random task graphs are optimized for each architecture, and evaluated with simulations. The energy versus performance trade-off is analyzed by looking at Pareto optimal solutions. It is assumed that there is a variety of processing elements whose number, frequency and microarchitecture can be modified for exploration purposes. It is found that both energy-efficient and well performing solutions exist, and in general, performance is traded for energy-efficiency. Results indicate that automated exploration tools are needed when the complexity of the mapping problem grows, starting already with our experiment setup: 6 types of PEs to select from, and the system consists of 2 to 5 PEs. Our results indicate that our Simulated Annealing method can be used for energy optimization with heterogeneous architectures, in addition to performance optimization with homogeneous architectures.
Keywords
microprocessor chips; multiprocessing systems; performance evaluation; simulated annealing; Pareto optimal solution; design space exploration; energy optimization; energy-efficient architecture; heterogeneous multiprocessor architecture evaluation; microarchitecture; performance optimization; processing element; simulated annealing; task graphs; Computer architecture; Energy consumption; Energy efficiency; Frequency; Hardware; Optimization; Pareto analysis; Simulated annealing; Space exploration; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2008. SOC 2008. International Symposium on
Conference_Location
Tampere
Print_ISBN
978-1-4244-2541-9
Electronic_ISBN
978-1-4244-2542-6
Type
conf
DOI
10.1109/ISSOC.2008.4694884
Filename
4694884
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