Title :
Design of a BIST RAM with row/column pattern sensitive fault detection capability
Author :
Franklin, Manoj ; Saluja, Kewal K. ; Kinoshita, Kozo
Author_Institution :
Wisconsin Univ., Madison, WI, USA
Abstract :
A novel fault model is developed for random-access memories for a class of pattern-sensitive faults called row/column weight-sensitive faults. A test procedure is developed to detect faults from the defined fault model. This test sequence also tests the memory array for the 5-cell-neighborhood static pattern-sensitive faults and other faults, such as stuck-at-faults and coupling faults. A built-in self-test (BIST) version of the algorithm has been implemented by completing the logic design and layout in 2-μm CMOS technology. The silicon area overhead for a 4M RAM is as little as 0.8%. The number of extra pins can be as low as one if clock is available on-chip. The number of extra pins can be as low as one if clock is available on-chip. The delay introduced to the normal paths, as estimated by simulation tools, is small and can be reduced even further
Keywords :
CMOS integrated circuits; automatic testing; computer equipment testing; fault location; integrated circuit testing; integrated memory circuits; logic arrays; logic design; logic testing; random-access storage; BIST RAM; CMOS technology; Si; algorithm; built-in self-test; coupling faults; delay; fault model; logic design; memory array; pattern-sensitive faults; random-access memories; row/column weight-sensitive faults; simulation; stuck-at-faults; Built-in self-test; CMOS technology; Clocks; Delay estimation; Fault detection; Pins; Random access memory; Read-write memory; Semiconductor device modeling; Testing;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82316
