Low power 6T-SRAM

This paper focuses on minimizing the Power consumption during Write and Standby operations and delay during Write in a 6T-SRAM cell by using a new Proposed architectural design in 32 nm technology and comparing the results with the architectural designs being used nowadays. As microprocessors and other electronics applications get faster and faster, the need for large quantities of data at very high speeds increases. Static Random Access Memory (SRAM) is an important memory device which stores data on a chip. SRAM acts as a Cache memory - providing a direct interface with the CPU at a speed which can never be attained by DRAMs. The Proposed 6-T architecture of SRAM cell is designed and implemented using 32 nm CMOS technology and results have been compared with the existing architectures which are widely in use. The results shows approx. 7.7% and 26% improvement in Power consumption during `Write operation´ and `Standby condition´ respectively and significant decrease in `Write delay´ apart from 31% improvement in terms of `Area´ of the chip used. The Proposed architecture has been designed and simulated by Microwind 3.1 software.