Title :
Designing highly integrated systems with gigabit/second CMOS serial transceiver cores
Author :
Nakamura, Karl ; Hovey, Rich
Author_Institution :
Dept. of Eng., LSI Logic Corp., Milpitas, CA, USA
Abstract :
Gigabit per second serial interconnects are gaining prominence with the adoption of serial interconnect standards such as Fibre Channel and Gigabit Ethernet. The availability of CMOS transceiver cores allows the system designer to integrate the gigabit physical layer with higher protocol layers, thereby achieving a low cost, low power solution. This paper examines ASIC design with CMOS gigabit transceiver cores, package selection, and board layout considerations for systems employing gigabit per second interconnects
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; integrated circuit design; transceivers; CMOS transceiver core; Fibre Channel; Gigabit Ethernet; board layout; high-speed serial interconnect; integrated system; low power ASIC design; package selection; protocol; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Clocks; Large scale integration; Packaging; Power system interconnection; Transceivers; Transmitters;
Conference_Titel :
Wescon/97. Conference Proceedings
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4303-4
DOI :
10.1109/WESCON.1997.632365
