DocumentCode :
1624379
Title :
The analysis of parallel BIST by the combined Markov chain (CMC) model
Author :
Chuang, C.C. ; Gupta, A.K.
Author_Institution :
Digital Equip. Corp., Marlboro, MA, USA
fYear :
1989
Firstpage :
337
Lastpage :
343
Abstract :
It is shown that the simple Markov chain model used to define the parallel BIST (built-in self-test) technique (see K. Kim et al., IEEE Trans. CAD Integrated Circuits Syst., p.919-28, Aug. 1988) does not work well for state machines. Instead, a combined Markov chain (CMC) model is proposed to analyze the behavior of state machines. It is shown that the feedback loop from the state registers, as well as the state assignments, can adversely affect the characteristics of the patterns generated by the state registers configured as signature analyzers. On the basis of this analysis, there has been developed a new state assignment algorithm that removes the adverse effects of feedback and ensures high controllability. This allows the use of the parallel BIST technique for state machines
Keywords :
Markov processes; VLSI; automatic testing; feedback; integrated circuit testing; integrated logic circuits; logic testing; IC testing; Markov chain model; VLSI; combined Markov chain; controllability; feedback loop; logic testing; parallel BIST; signature analyzers; state assignment algorithm; state machines; state registers; Built-in self-test; Circuit testing; Controllability; Design for testability; Logic testing; Pattern analysis; Registers; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
Type :
conf
DOI :
10.1109/TEST.1989.82317
Filename :
82317
Link To Document :
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