Title :
Design issues in digit serial signal processors
Author :
Irwin, Mary Jane ; Owens, Robert Michael
Author_Institution :
Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Several design issues that have arisen during the development of a set of CAD tools used to support the rapid prototyping of a family of VLSI signal processing architectures are presented. The components out of which the signal processors are constructed are ones which operate digit-serially. Digit-serial architectures, which have digit-serial data transmission combined with digit-serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit-serial input are overcome if the input is overlapped with the computation (referred to as digit pipelining). Thus, digit-serial architectures can provide both high throughput and low latency. Design tradeoffs affecting the component design as well as the system design for digit serial signal processors are presented. Considerations which have affected the development of CAD tools are discussed
Keywords :
VLSI; circuit CAD; digital signal processing chips; pipeline processing; CAD tools; VLSI signal processing architectures; digit pipelining; digit serial signal processors; digit-serial architectures; digit-serial computation; digit-serial data transmission; latency; prototyping; throughput; Data communication; Delay; Design automation; Pipeline processing; Process design; Prototypes; Signal design; Signal processing; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100385