Testability analysis of synchronous sequential circuits based on structural data

Test sequence length is an effective measure of testability of a sequential circuit. The lower the bound on the length, the more testable the circuit is. A graph-theoretic approach is used to compute the bound on test sequence length for any sequential circuit. The condensation of the graph is found by collapsing the strongly connected components into single nodes. By analyzing each stem region, it is possible to compute the bound on test sequence length for the entire circuit. The time complexity of the procedure is O(n²), where n is the number of nodes in the circuit graph. The bounds of the individual submachines can be used in test generation, scan design, and built-in self-test design. Three design rules are specified to yield circuits with lower test sequence bounds